16-bit Booth Multiplier with 32-bit Accumulate
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Joined: Sep 2010
07-10-2010, 11:48 AM
This report presents three main topics we investigated as part of a project and implimentation to build a Booth encoded multiply/accumulate VLSI chip. The original scope of work included synthesizing VHDL code using the Mentor Graphics tools. Exemplar was the VHDL compiler. Leonardo Spectrum was the synthesizer. Since my team, which included Kevin Delaney, did not meet a Mosis deadline our chip funding was lost. Since we did not actually fabricate a chip, we cannot discuss the success of our results. Likewise, VHDL synthesis using the Exemplar tools was not very successful, so we do not discuss synthesis results except in passing. The main points we cover are the basic architecture, our VHDL code, and a Magic layout in place of logic synthesis. The work presented here, except as cited, is almost entirely my own. Teamwork with Kevin Delaney had some influence on the VHDL code, since he was primarily working on the synthesis portion of the project and implimentation.
Due to length considerations, we have not included all VHDL code or any test suites. We have attached VHDL code for our main modules. We have not included any of the test scripts or stimulus files. They are available on-line or via the CSE file system. They are very similar to other work we have submitted. We have also excluded material previously reported in our report of Spring 2000.
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