3D Stacking: EDA Challenges & Opportunities
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20-10-2010, 10:12 AM

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3D Stacking: EDA Challenges & Opportunities

SEMATECH SymposiumTokyo, Japan
Rajiv MaheshwarySenior Director


3D IC Market Drivers
–Cost, Performance/Power
–Heterogeneous integration
•Customers expected to have production devices starting 2011
–Logic + DRAM and Logic + Logic
–$20B* TSV devices by 2013
•Synopsys Focus
–Enable design flow with partners
–Lead definition of emerging interoperability standards

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