Application of DDR Controller for High-speed Data Acquisition Board
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19-10-2010, 05:34 PM
This article describes a DDR SDRAM (Double Data Rate Synchronously
Dynamic RAM) controller. The commands of the FPGA-based DDR
SDRAM controller is described in detail. The Verilog HDL is used to implement the R/W operation of the DDR SDRAM. This controler isused to control a 400MHz single channel high-speed, high-precision and large-capacity data acquisition board.
The speed and precision of data acquisition system must be sufficiently high to meet the requirements of advanced communication technology development. high data throughput ratio is a feature which is basic and there also arises the need to transmit and storing the result for a short time. The system speed and time tolerance are the limiting factors .
DDR SDRAM is an enhancement to the traditional synchronous DRAM. The data can be transferred in the both the edges of the each clock cycle. Thus the data throughput of the memory device is doubled. PCs widely uses it for its low cost. A DDR controller for an SDRAM device is designed in this article.
high-speed data acquisition board
A A/D converter, FPGA, DDR SDRAM and PCI bridge are the main components of the data acquisition board. The FPGA has integrated on it DDR controller, bi-channel input FIFO and single channel output FIFO.
A synchronous command interface is provided to the SDRAM by the DDR SDRAM Controller. The commands are:
NOP,READA ,WRITEA ,REFRESH , PRECHARGE , LOAD_MODE, LOAD_REG1
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