Compact and EFficient encryption and decryption
Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
project report helper
Active In SP

Posts: 2,270
Joined: Sep 2010
20-10-2010, 10:21 AM

.pdf   7_compact_and_efficient_encryption-decryption_module_for_fpga.pdf (Size: 243.64 KB / Downloads: 68)

Compact and Efcient Encryption/Decryption Module for
FPGA Implementation of the AES Rijndael
VeryWell Suited for Small Embedded Applications

Ga¨el Rouvroy, Franc¸ois-Xavier Standaert,
Jean-Jacques Quisquater and Jean-Didier Legat
UCL Crypto Group
Laboratoire de Micro´electronique
Universit´e catholique de Louvain
Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium

Hardware implementations of the Advanced Encryption
Standard (AES) Rijndael algorithm have recently
been the object of an intensive evaluation. Several
papers describe efcient architectures for ASICs1
and FPGAs2. In this context, the highest effort was devoted
to high throughput (up to 20 Gbps) encryptiononly
designs, fewer works studied low area encryptiononly
architectures and only a few papers have investigated
low area encryption/decryption structures.
However, in practice, only a few applications need
throughput up to 20 Gbps while exible and low cost
encryption/decryption solutions are needed to protect
sensible data, especially for embedded hardware applications.
This paper proposes an efcient solution
to combine Rijndael encryption and decryption in one
FPGA design, with a strong focus on low area constraints.
The proposed design ts into the smallest Xilinx
FPGAs3, deals with data streams of 208 Mbps,
uses 163 slices and 3 RAM blocks and improves by
68% the best-known similar designs in terms of ratio
Throughput=Area. We also propose implementations
in other FPGA Families (Xilinx Virtex-II) and
comparisons with similar DES, triple-DES and AES


In October 2000, NIST (National Institute of Standards
and Technology) selected Rijndael [4] as the new
Advanced Encryption Standard (AES), in order to replace
the old Data Encryption Standard (DES). The
selection process included performance evaluation on
both software and hardware platforms and many hardware
architectures were proposed. However, most of
these architectures simply transcript the algorithm into
hardware designs, without relevant optimizations and
tradeoffs. Moreover, the throughput and area constraints
considered are often unrealistic as shown by
the recently published results.
First, many very high-speed ( 10 Gbps) cipher
hardware implementations have been published in the
literature. These designs consists of FPGA implementations
of a complete unrolled and pipelined cipher.
The best such DES implementation is an encryptor/
decryptor based on a new mathematical description.
It can achieve data rates of 21.3 Gbps in Virtex-II
FPGAs [15]. The encryption/decryption mode can be
changed on a cycle-by-cycle basis with no dead cycles.
For the AES, the best similar RAM-based solution
unrolls the 10 cipher rounds and pipelines them
in an encryption-only process. This implementation in
a Virtex-E FPGA produces a throughput of 11.8 Gbps
[17, 18] and allows the key to be changed at every cycle.
This DES implementation reaches higher throughput
than the corresponding AES implementation.

Important Note..!

If you are not satisfied with above reply ,..Please


So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Tagged Pages: for seminar encryption and decryption ppt, seminar topics for encryption and decryption, seminar topics based on encryption and decryption, project topic on encryption and decryption, rouvroy standaert pdf, encryption and decryption project report, ppt on pipelined aes,
Popular Searches: project on dna based encryption and decryption, application of new framework for high secure data hidden in the mpeg using aes encryption algorithm, encryption and decryption pdf, text file encryption and decryption over network java based project abstract, seminar about encryption and decryption, class diagram for encryption and decryption of text, aes implimentation on fpga,

Quick Reply
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  XML encryption full report computer science technology 7 6,631 24-03-2014, 02:31 PM
Last Post: seminar project topic
  Intrusion Detection: An Energy Efficient Approach in Heterogeneous WSN pdf study tips 1 924 09-02-2014, 05:40 PM
Last Post: Guest
  Going Back and Forth: Efficient Multideployment and Multisnapshotting on Clouds pdf seminar projects maker 0 273 24-09-2013, 04:00 PM
Last Post: seminar projects maker
  International Data Encryption Algorithm Report study tips 0 527 22-08-2013, 04:55 PM
Last Post: study tips
  Efficient SCADA Module for Improving Medical Information Monitoring and Reliable pdf study tips 0 342 22-08-2013, 03:04 PM
Last Post: study tips
  Report on Exploiting Dynamic Resource Allocation for Efficient Parallel Data study tips 0 364 21-08-2013, 04:36 PM
Last Post: study tips
  VLSI Realization of a Secure Cryptosystem for Image Encryption and Decryption pdf study tips 0 517 20-08-2013, 04:51 PM
Last Post: study tips
Last Post: study tips
  REPORT ON ENCRYTION/ DECRYPTION ALGORITHM study tips 0 259 12-07-2013, 12:50 PM
Last Post: study tips
  Enabling Secure and Efficient Ranked Keyword Search over Outsourced Cloud Data pdf study tips 0 443 09-07-2013, 03:46 PM
Last Post: study tips