DSP Processor
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computer science crazy
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21-09-2008, 11:01 AM

The best way to understand the requirements is to examine typical DSP algorithms and identify how their compositional requirements have influenced the architectures of DSP processor. Let us consider one of the most common processing tasks the finite impulse response filter.

For each tap of the filter a data sample is multiplied by a filter coefficient with result added to a running sum for all of the taps .Hence the main component of the FIR filter is dot product: multiply and add .These options are not unique to the FIR filter algorithm; in fact multiplication is one of the most common operation performed in signal processing -convolution, IIR filtering and Fourier transform also involve heavy use of multiply -accumulate operation. Originally, microprocessors implemented multiplication by a series of shift and add operation, each of which consumes one or more clock cycle .First a DSP processor requires a hardware which can multiply in one single cycle. Most of the DSP algorithm require a multiply and accumulate unit (MAC).

In comparison to other type of computing tasks, DSP application typically have very high computational requirements since they often must execute DSP algorithms in real time on lengthy segments ,therefore parallel operation of several independent execution units is a must -for example in addition to MAC unit an ALU and shifter is also required .
Executing a MAC in every clock cycle requires more than just single cycle MAC unit. It also requires the ability to fetch the MAC instruction, a data sample, and a filter coefficient from a memory in a single cycle. Hence good DSP performance requires high memory band width-higher than that of general microprocessors, which had one single bus connection to memory and could only make one access per cycle. The most common approach was to use two or more separate banks of memory, each of which was accessed by its own bus and could be written or read in a single cycle. This means programs are stored in a memory and data in another .With this arrangement, the processor could fetch and a data operand in parallel in every cycle .since many DSP algorithms consume two data operands per instruction a further optimization commonly used is to include small bank of RAM near the processor core that is used as an instruction cache. When a small group of instruction is executed repeatedly, the cache is loaded with those instructions, freeing the instruction bus to be used for data fetches instead of instruction fetches -thus enabling the processor to execute a MAC in a single cycleHigh memory bandwidth requirements are often further supported by dedicated hard ware for calculating memory address. These memory calculating units operate in parallel with DSP processors main execution units, enabling it to access data in new location in the memory without pausing to calculate the new address.

Memory accesses in DSP algorithm tend to exhibit very predictable pattern: for example For sample in FIR filter , the filter coefficient are accessed sequentially from start to finish , then accessed start over from beginning of the coefficient vector when processing the next input sample .This is in the contrast of other computing tasks ,such as data base processing where accesses to memory are less predictable .DSP processor address generation units take advantage of this predictability of supporting specialize addressing modes that enable the processor to efficiently access data in the patterns commonly found in DSP algorithms .The most common of these modes is register indirect addressing with post increment , which is used to automatically increment the address pointer for the algorithms where repetitive computations are performed on a series of data stored sequentially in the memory .Without this feature , the programmer would need to spend instruction explicitly incrementing the address pointer .
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11-08-2010, 07:12 AM

please give me ppt of this topc
seminar flower
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31-05-2012, 03:19 PM

DSP Processor

.ppt   DSP Processor.ppt (Size: 287.5 KB / Downloads: 65)

High speed DSP computations
Specialized instruction set
High performance repetitive numeric calculations
Fast & efficient memory accesses

Special mechanism for real-time I/O
Low power consumption
Low cost in comparison with GPPs

DSPs μPs Applications

Speech and audio compression
Modulation and demodulation
Error correction coding and decoding
Audio processing (e.g., surround sound, noise reduction, equalization, sample rate conversion, echo cancellation)
Signaling (e.g., DTMF detection)
Speech recognition
Signal synthesis (e.g., music, speech synthesis).

DSPs Characteristics

Data path & internal ALU architecture
Specialized instruction set
External memory architecture
Specialized addressing modes
Specialized execution control
Specialized peripherals for DSP


Very long instruction word (VLIW) architectures are garnering increased attention for DSP applications.

Major features:
Multiple independent operations per cycle
Packed into a single large “instruction” or “packet”
More regular, orthogonal, RISC-like operations Large, uniform register sets
seminar flower
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17-08-2012, 05:00 PM


.pptx   DSP processor.pptx (Size: 481.85 KB / Downloads: 22)

Digital Signal Processors…

DSPs are microcontrollers specifically designed to handle digital signal processing tasks and are deployed in a variety of applications like hard disk controllers, cellular phones, speech recognition systems etc.
Commonly used operations in signal processing applications are convolution, filtering, and frequency-time domain conversions need recursive multiplication and additions i.e multiply and accumulate (MAC) operations; main fuction by DSP processors. .
VendorsAnalog Devices, Motorola, Texas instruments


VLIW(very long instruction word) ARCHITECTURE


The DSK features the TMS320C6713 DSP, for applications that require high precision accuracy. The C6713 is based on the  TMS320C6000 DSP platform designed to needs of high-performing high-precision applications such as pro-audio, medical and diagnostic. Other hardware features of the TMS320C6713 DSK board include:
Embedded JTAG support via USB
High-quality 24-bit stereo codec
Four 3.5mm audio jacks for microphone, line in, speaker and line out
512K words of Flash and 16 MB SDRAM
Expansion port connector for plug-in modules
On-board standard IEEE JTAG interface
+5V universal power supply
Software - Designers can readily target the TMS32C6713 DSP through TI´s robust and comprehensive Code Composer Studio™ DSK development platform. Code Composer Studio features for the TMS320C6713 DSK include:
A complete Integrated Development Environment (IDE), an efficient optimizing C/C++ compiler assembler, linker, debugger, an a advanced editor with Code Maestro™ technology for faster code creation, data visualization, a profiler and a flexible project and implimentation manager
DSP/BIOS™ real-time kernel


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