Design of a Low-Power High-Speed Current Comparator in 0.35-μm CMOS Technology
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Design of a Low-Power High-Speed Current Comparator
in 0.35-μm CMOS Technology

Soheil Ziabakhsh1, Hosein Alavi-Rad1,
1Electrical Engineering, University of Guilan,
2Electrical Engineering Department,
3Engineering & Science Department, Sharif University of Technology, International Campus, Kish, Iran


A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology.

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