FPGA Implementation(s) of a Scalable Encryption Algorithm
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Joined: Oct 2010
19-10-2010, 05:17 PM
SEA is a scalable encryption algorithm targeted for small embedded applications. controllers, smart cards or processors software implementation was the target of SEA when it was introduced. its performances in recent FPGA
devices is discussed here. A loop architecture of the block cipher is presented in order to do this. full flexibility for any parameter is an advantage of this system other than its low cost. generic VHDL coding is used here. The small area requirements are also kept. SEA is also compard with the similar algorithms like Standard Rijndael and ICEBERG.
SEA is a parametric block cipher for resource constrained systems like sensor networks, RFIDs etc. processors with a limited instruction set like AND, OR , XOR etc was the main target of SEA. The algorithm accepts the plaintext, key and the bus sizes as the parameters and can be straightforwardly adapted to various implementation contexts.
embedded software applications using microcontrollers can benefit from this technique. The algorithm’s scalability is turned into a fully generic VHDL design. With this , the bus size, plaintext , and key can be easily varied and re-implemented without any software modifications.
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