Field-programmable gate array
Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
computer science crazy
Super Moderator

Posts: 3,048
Joined: Dec 2008
24-02-2009, 12:45 AM

field-programmable gate array is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. A hierarchy of programmable interconnects allows logic blocks to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. Logic blocks and interconnects can be programmed by the customer or designer, after the FPGA is manufactured, to implement any logical function”hence the name "field-programmable". FPGAs are usually slower than their application-specific integrated circuit (ASIC) counterparts, cannot handle as complex a design, and draw more power (for any given semiconductor process). But their advantages include a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The designs are developed on regular FPGAs and then migrated into a fixed version that more resembles an ASIC. "Complex Programmable Logic Device" (CPLDs) are an alternative for simpler designs. They also retain their programming over powerdowns. To configure ("program") an FPGA or CPLD you specify how you want the chip to work with a logic circuit diagram or a source code using a hardware description language (HDL). The HDL form might be easier to work with when handling large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. On the other hand, schematic entry can allow for easier visualisation of a design. Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then transferred to the FPGA/CPLD via a serial interface (JTAG) interface or to external memory device like an EEPROM.
Use Search at wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion

Important Note..!

If you are not satisfied with above reply ,..Please


So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Tagged Pages: field programmable gate array, programmable seminar topics, download abstract for seminar for field programming gate array, seminar on complex logic gate,
Popular Searches: isfet array, field programmable radio, railyway gate, exor gate by or gate, gate security systemscrossing, working ex or gate, design of fuzzy logic controller for ac motor based on field programmable gate array,

Quick Reply
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  coin based toll gate system jaseelati 0 229 23-01-2015, 03:49 PM
Last Post: jaseelati
  Introduction to Programmable Peripheral Interface 8255 study tips 0 354 10-09-2013, 03:50 PM
Last Post: study tips
  GATE Syllabus for Electronics and Communication Engineering (ECE) study tips 0 455 28-08-2013, 04:05 PM
Last Post: study tips
  Programmable Peripheral Interface ppt study tips 0 247 22-06-2013, 04:33 PM
Last Post: study tips
  Field-programmable gate arrays (FPGAs) pdf study tips 0 425 05-06-2013, 04:31 PM
Last Post: study tips
  TECHNICAL SEMINAR ON PHASED ARRAY RADAR ANTENNA study tips 0 469 03-06-2013, 04:36 PM
Last Post: study tips
  REPORT ON FOUNDATION FIELD BUS study tips 0 315 08-05-2013, 03:44 PM
Last Post: study tips
Last Post: study tips
  Construction of Optimum Composite Field Architecture for Compact High-Throughput AES study tips 0 411 16-04-2013, 03:03 PM
Last Post: study tips
  Microprocessor System Design Programmable Interrupt Controller PPT study tips 0 403 05-03-2013, 03:19 PM
Last Post: study tips