New Non-Volatile Memory Structures for FPGA Architectures
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29-10-2010, 09:00 AM

New Non-Volatile Memory Structures for FPGA Architectures
Presented by:
Haseen PP
S7 applied Electronics
College Of Engineering, Trivandrum
2007-11 batch

.ppt   New Non-Volatile Memory Structures for FPGA Architectures.ppt (Size: 590 KB / Downloads: 46)
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Non-Volatile Device Structure
Experimental device characteristics
New PE for routing switches
New PE for configuration of logical elements
New Non-Volatile flip-fop


FPGA experienced dramatic increase in speed, size, flexibility, performance per cost, & commercial impact the early 1990’s
They can be generally classified according to type the of memory structure used
SRAM-based FPGAs(by Xilinx and Altera), Flash-based FPGAs(by Actel)
SRAM-based FPGAs are generally fast, but volatile in nature and configuration require high current
In Flash-based FPGAs configuration data can retain even when power is off

Speed of programming --> Desired Level of threshold shift
Dependent on source voltage(Range 0-3 V)
By detecting the level of threshold shift
Using the F-N tunneling mechanism

New PE for routing switches

PE – Non-Volatile device coupled with word-line transistor and small pull down transistor
Current flow in non-volatile device – present during erased state and absent during programmed state
Input supply of 0-3 V
Raise the word-line voltage
Supply of 0 V to fgy
Biasing the control gate, select gate and drain lines

PE for the configuration of logical elements
Storage of data
Data is placed on the input port and the word line is turned high
N-MOS latch is allowed to change its state to low-high or high-low
Programming voltages are applied to control gate, select gate and drain
Source nodes are tied to complementary nodes m and mb

On power turn-off –
Data on the nMOS latch loses relevance

On power turn-on –
Non volatile device that is erased will conduct current
Non volatile device that is programmed will not conduct
Differential current – used to restore the state of the nMOS latch and to supply and replace any charge lost through sub-threshold leakage

New Non-Volatile flip-flop
Two additional non-volatile devices attached to the m and mb nodes of the SRAM cell
WR signal – write control signal for the flip-flop
During power failure, latch data is used to program the two non-volatile devices
When power is restored, only the erased device conducts current
Uses –
Storing of state information in a state machine
Storing of pipelined data

Power Consumption Strategies
Some or all of the FPGA can be put into sleep mode or be powered down completely
FPGA can be either locally or globally powered down
Standby power of FPGAs can be hundreds of milli watts even in low power designs
Application – Template/Pattern matching

Low programming current- Many devices can be programmed at the same time, in parallel
Large area savings, reduced mask count
Comparable speeds to SRAM-based FPGAs
Ability to store data in absence of power
Cost savings
Lower power in-system re-programmability


Presented a set of new designs for core FPGA logic, routing, and flip-flop circuits
Got advantages both SRAM-based and Flash based
FPGA architecture using core FPGA elements described here offer the potential to dramatically improve power efficiency, speed, area, and cost
Enabled by non-volatile device that has the advantage of a low programming current

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