Radiation hardening by design (RHBD)
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sunil kr.verma
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07-10-2010, 04:12 PM

full report on Radiation hardening chips
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27-10-2010, 10:14 AM

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity.

The objective of the Radiation Hardening by Design (RHBD) program is to develop and demonstrate design and layout techniques to support the fabrication of strategically radiation hardened integrated circuits from pure design approaches; no changes in fabrication or materials. The program is focused on foundry-type silicon technologies, ultra-deep submicron (e.g. < 90 nm technology) geometries, and digital / analog / mixed signal integrated circuits. Specific interest is in the demonstration of design techniques for producing radiation hardened devices on standard commercial foundry flows, without any modification of the existing process or violation of design and layout rules, with corresponding electrical performance and area penalties of less than or equal to one fabrication generation.

Radiation effects in space or even at higher altitudes of the earth's atmosphere can degrade semiconductor microelectronic and photonic devices and circuits. This is becoming increasingly relevant as technologies continue to evolve toward higher levels of integration and circuit complexity. CFDRC ADS offers scientific/engineering expertise and advanced modeling tools in Micro- and Nano-Electronics domains, for analysis of radiation effects from both single-event (ion strike) and total-dose radiation phenomena in devices and circuits. This work includes, but is not limited to:

Micro & Nano-scale Device Physics
Space Radiation Effects Simulation
Radiation Hardening
3D Ion Track Visualization
Radiation Analysis from IC Design
Single Event Modeling with Nuclear Reactions
Extreme Environments (Low & High Temperatures)

In RHBD, electronic components are manufactured to meet specified radiation performance criteria, but the techniques employed to meet these criteria are implemented either in layout or in the application architecture and not in the fabrication process. RHBD is typically considered distinct from radiation-hardening-by-process (RHBP). Radiation hardening via process modifications is the traditional approach used by rad-hard foundries (although it should be noted that these foundries typically implement both RHBP and RHBD techniques). While RHBP has the advantage of being an extremely reliable means of achieving hardened components, RHBP is susceptible to low volume concerns such as yield, process instability, and high manufacturing costs. These drawbacks, when coupled with the post Cold War contraction of the government electronics market, caused a dramatic industrial exodus from rad-hard manufacturing. The number of rad-hard foundries has gone from more than ten in 1985 to two dedicated foundries today.


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