Reduced Instruction Set Computer (RISC) processor
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22-10-2010, 04:06 PM

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Reduced Instruction Set Computer (RISC) processor


This project and implimentation is aimed at designing of a Reduced Instruction Set Computer (RISC) processor using the Verilog Hardware Description Language (HDL). For a long time, programming languages such as C, Pascal & FORTRAN were being used to describe the computer programs that were sequential in nature. Similarly in the digital design field, designers felt the need for a standard language to describe digital circuits. Thus, HDL came into existence. HDL allowed the designers to model the concurrency of processes found in hardware elements.
In this project and implimentation we took the RISC processor as a task. Basically the RISC processors are easy to learn because it has very less but power full instruction sets. And also it has so many internal peripherals. So using the RISC processor the hardware designs become very compact and cost effective.

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