Seminar on 3- D ICs
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20-09-2009, 04:22 PM

3- D ICs



The unprecedented growth of the computer and the Information

technology industry is demanding Very Large Scale Integrated (VLSI) circuits

with increasing functionality and performance at minimum cost and power

dissipation. VLSI circuits are being aggressively scaled to meet this Demand,

which in turn has some serious problems for the semiconductor industry.

Additionally heterogeneous integration of different technologies in one

single chip (SoC) is becoming increasingly desirable, for which planar (2-D) ICs

may not be suitable.

3-D ICs are an attractive chip architecture that can alleviate the

interconnect related problems such as delay and power dissipation and can also

facilitate integration of heterogeneous technologies in one chip (SoC). The

multi-layer chip industry opens up a whole new world of design. With the

Introduction of 3-D ICs, the world of chips may never look the same again.



There is a saying in real estate; when land get expensive, multi-storied

buildings are the alternative solution. We have a similar situation in the chip

industry. For the past thirty years, chip designers have considered whether

building integrated circuits multiple layers might create cheaper, more powerful


Performance of deep-sub micrometer very large scale integrated (VLSI)

circuits is being increasingly dominated by the interconnects due to increasing

wire pitch and increasing die size. Additionally, heterogeneous integration of

different technologies on one single chip is becoming increasingly desirable, for

which planar (2-D) ICs may not be suitable.

The three dimensional (3-D) chip design strategy exploits the vertical

dimension to alleviate the interconnect related problems and to facilitate

heterogeneous integration of technologies to realize system on a chip (SoC)

design. By simply dividing a planar chip into separate blocks, each occupying a

separate physical level interconnected by short and vertical interlayer

interconnects (VILICs), significant improvement in performance and reduction

in wire-limited chip area can be achieved.

In the 3-Ddesign architecture, an entire chip is divided into a number of

blocks, and each block is placed on a separate layer of Si that are stacked on top

of each other.



The unprecedented growth of the computer and the information

technology industry is demanding Very Large Scale Integrated ( VLSI ) circuits

with increasing functionality and performance at minimum cost and power

dissipation. Continuous scaling of VLSI circuits is reducing gate delays but

rapidly increasing interconnect delays. A significant fraction of the total power

consumption can be due to the wiring network used for clock distribution, which

is usually realized using long global wires.

Furthermore, increasing drive for the integration of disparate signals

(digital, analog, RF) and technologies (SOI, SiGe, GaAs, and so on) is

introducing various SoC design concepts, for which existing planner (2-D) IC

design may not be suitable.


In single Si layer (2-D) ICs, chip size is continuously increasing despite

reductions in feature size made possible by advances in IC technology such as

lithography and etching. This is due to the ever growing demand for functionality

and high performance, which causes increased complexity of chip design,

requiring more and more transistors to be closely packed and connected. Small

feature sizes have dramatically improved device performance. The impact of this

miniaturization on the performance of interconnect wire, however, has been less

positive. Smaller wire cross sections, smaller wire pitch, and longer line to

traverse larger chips have increase the resistance and capacitance of these lines,

resulting in a significant increase in signal propagation (RC) delay. As

interconnect scaling continues, RC delay is increasingly becoming the dominant

factor determining the performance of advanced ICâ„¢s.



At 250 nm technology node, Cu with low-k dielectric was introduced to

alleviate the adverse effect of increasing interconnect delay.However,below

130nm technology node, substantial interconnect delays would result in spite of

introducing these new materials, which in turn will severely limit the chip

performance. Further reduction in interconnect delay is not possible.

This problem is especially acute for global interconnects, which comprise

about 10% of total wiring in current architectures. Therefore, it is apparent that

material limitations will ultimately limit the performance improvement as

technology scales. Also, the problem of long lossy lines cannot be fixed by

simply widening the metal lines and by using thicker interlayer dielectric, since

this will leas to an increase in the number of metal layers. This will result in an

increase in complexity, reliability and cost.


System “ on “ a “chip (SoC) is a broad concept that refers to the

integration of nearly all aspects of a system design on a single chip. These chips

are often mixed-signal and/or mixed-technology designs, including such diverse

combinations as embedded DRAM, high “ performance and low-power logic,

analog, RF, programmable platforms (software, FPGAs, Flash, etc.).

SoC designs are often driven by the ever-growing demand for increased

system functionality and compactness at minimum cost, power consumption, and

time to market. These designs form the basis for numerous novel electronic

applications in the near future, in areas such as wired and wireless multimedia

communications including high speed internet applications, medical applications

including remote surgery, automated drug delivery, and non invasive internal

scanning and diagnosis, aircraft/automobile control and safety, fully automated

industrial control systems, chemical and biological hazard detection, and home

security and entertainment systems, to name a few.

There are several challenges to effective SoC designs:

1. Large scale integration of functionalities and disparate technologies on a

single chip dramatically increases the chip area, which necessitates the use of

numerous long global wires. These wires can lead to unacceptable signal

transmission delays and increase the power consumption by increasing the

total capacitance that needs to be driven by the gates.

2. Integration of disparate technologies such as embedded DRAM, logic, and

passive components in SoC applications introduces significant complexity in

materials and process integration.

3. The noise generated by the interference between different embedded circuit

blocks containing digital and analog circuits becomes a challenging problem.

4. Although SoC designs typically reduce the number of I/O pins compared to a

system assembled on a printed circuit board(PCB), several high performance

SoC designs involve very high I/O pin counts , which can increase the cost

per chip

5. Integration of mixed technologies on a single die requires novel design

methodologies and tools ,with design productivity being a key requirement.


Three-dimensional integration to create multilayer Si ICs is a concept that

can significantly improve interconnect performance ,increase transistor packing

density, and reduce chip area and power dissipation. Additionally 3D ICs can be

very effective large scale on chip integration of different systems.

In 3D design architecture, and entire(2D) chips is divided into a number

of blocks is placed on separate layer of Si that are stacked on top of each other.

Each Si layer in the 3D structure can have multiple layer of

interconnects(VILICs) and common global interconnects.



The 3D architecture offers extra flexibility in system design, placement

and routing. For instance, logic gates on a critical path can be placed very close

to each other using multiple active layers. This would result in a significant

reduction in RC delay and can greatly enhance the performance of logical


The 3D chip design technology can be exploited to build SoCs by placing

circuits with different voltage and performance requirements in different


The 3D integration can reduce the wiring ,thereby reducing the

capacitance, power dissipation and chip area and therefore improve chip


Additionally the digital and analog components in the mixed-signal

systems can be placed on different Si layers thereby achieving better noise

performance due to lower electromagnetic interference between such

circuits blocks.

From an integration point of view, mixed-technology assimilation could

be made less complex and more cost effective by fabricating such

technologies on separate substrates followed by physical bonding.



A 3D solution at first glance seems an obvious answer to the interconnect

delay problem. Since chip size directly affects the inter connect delay, therefore

by creating a second active layer, the total chip footprint can be reduced, thus

shortening critical inter connects and reducing their delay. However, in todayâ„¢s

microprocessor, the chip size is not just limited by the cell size ,but also by how

much meta is required to connect the cells. The transistors on the Si surface are

not actually packed to maximum density, but are spaced apart to allow metal

lines above to connect one transistor or one cell to another .The meal required

on a chip for inter connections is determined not only by the number of gates

,but also by other factors such as architecture, average fan-out, number of I/O

connections, routing complexity, etc Therefore, it is not obvious that using a 3D

structure the chip size will be reduced.



Now we present a methodology that can be used to provide an initial

estimate of the area and performance of high speed logic circuits fabricated using

multiple silicon layer IC technology. The approach is based on the empirical

relationship known as Rentâ„¢s Rule.

Rentâ„¢s Rule:

It correlates the number of signal input and output (I/O) pins T, to the

number of gates N, in a random logic network and is given by the following

expressions :

T=kNP ””””-(i)

Here k & P denote the average number of fan out per gate and the degree of

wiring complexity (with P=1 representing the most complex wiring network),

respectively, and are empirically derived as constants for a given generation of



The wire-length distribution can be described by i(l),an interconnect

density functions (i.d.f), or by I(l), the cumulative interconnect distribution

function (c.i.d.f) which gives the total number of interconnects that have length

less than or equal to l (measured in gate pitches) and is defined as


I(l)= çl


i(x)dx ”””“(ii)

Where x is a variable of integration representing length and l is the length of the

interconnect in gate pitches. The derivation of the wire-length distributed in a Ic


is based on Rentâ„¢s Rule. To derive the wire length distribution I(l) of an

integrated circuit, the latter is divided up into N logic gates, where N is related to

the total number of transistor Nt in an integrated circuit by N=Nt/O where O is a

function of the average fan-in(f.i0 and fan-out(f.o). The gate pitch is defined as

the average separation between the logic gates and is equal to sqt(Ac/N) where

Ac is the area of the chip.

In order to derive the complete wire-length distribution for a chip, the

stochastic wire-length distribution of a single gate must be calculated.

The number of connections from the single logic gate in Block A to all

other gate that are located at a distance of l gate pitches is determined using

Rentâ„¢s Rule. The gates shown in the figure are grouped into three distinct but

adjacent blocks(A,B&C), such that a closed single path can encircle one, two or

three of these blocks. The number of connections between Block A and Block C

is calculated by conserving all I/O terminals for blocks, A, B, and C, which states

that terminals for blocks A, B, and C, are either interlock connections or external

system connections.


Hence, applying the principle of conservation of I/O pins to this system of

three logic blocks, shown gives

TA + TB + TC = TA to C + TA to B + TB to C + TABC ¦¦¦¦¦.(iii)

Where TA, TB, TC are the number of I/O blocks A, B, and C respectively.

TA to C , TA to B, TB to C are the number of I/Os between blocks A and C, blocks A

and B, and between blocks B and C, respectively. TABC represents the number

of I/Os for the entire system comprising of all three blocks. From conservation

of I/Os, the number of I /Os between adjacent blocks A and B, and between

adjacent blocks A and B and between adjacent blocks B and C can be expressed


TA to B = TA + TB - TAB ¦¦¦¦¦¦¦¦..¦¦.(iv)

TB to C = TB + TC “ TBC ..¦¦¦¦¦¦¦¦¦¦.(v)

Substituting (iv) and (v) into (iii) gives

TA to C = TAB + TBC “ TB - TABC ¦¦¦¦¦¦¦¦¦¦(vi)

Now the number of I/O pins for any single block or a group of blocks can

be calculated using Rentâ„¢s Rule. If we assume that N, N, and N are the number

of gates in blocks A, B, and C, respectively, then it follows that

TB = k (NB)P ¦¦¦¦¦¦¦¦¦(vii)

TAB = k(NA + NB)P ¦¦..¦¦¦¦¦¦..(viii)

TBC = k(NB + NC )P ¦¦¦.¦¦¦¦¦¦(ix)

TABC = k(NA + NB +NC)P ¦¦¦¦¦¦¦¦¦.(x)

Where N = NA + NB + NC. Substituting (vii) “ (x) into (vi) gives

TA to C = k [( NA + NB)P “ (NB)P + (NB + NC)P “ (NA + NB + NC)P] ¦¦..(xi)


The number of interconnects between Block A and Block C (IA to C) is

determined using the relation

IA to C = ak (TA to C)

Where a is related to the average fan out (f.o.) by

a = f.o. / (1+f.o.)

Applying Rentâ„¢s Rule to all the layers, we have

T=kNP = (??=


i 1

Ti) “ Tint = nk(N/n)P - Tint

Here, T is the number of I/Os for the entire design, Ti represents the number of

I/O ports connecting n layers. Hence it follows that

Tint = n (1- nP-1) k (N/n)P and

Text,i = Ti “ Tint/n = knP-1 (N/n)P

Here, Text,i , is the average of I/O ports per layer.


In integrated circuits that are wire-pitch limited in size, the area require by

the wiring network is assumed to be much greater than the area required by the

logic gates. For the purpose of minimizing silicon real estate and signal

propagation delays, the wiring network is segmented into separate tiers that are

physically fabricated in multiple layers.


An interconnect tier is categorized by factors such as metal line pitch and

cross-section, maximum allowable signal delay and communication mode (such

as intra block, or inter block). A tier can have more than one layer of metal

interconnects if necessary, and each tier or layer is connected to the rest of the

wiring network and the logic gates by vertical vias. The tier closest to the logic

devices (referred to as the local tier) is normally for short distance intra block


Metal lines in this tier will normally be the shortest. They will also

normally have the finest pitch. The tier furthest away from the device layer

(referred to as global tier) is responsible for long distance across chip inter block

communications, clocking and power distribution. Since this tier is populated by

the longest of wires, the metal pitch is the largest to minimize signal propagation

delays. A typical modern IC interconnects architecture will define three wiring

tiers: local, semi-global, and global. The semi-global tier is normally

responsible for inter block communications across intermediate distances.


The area of the chip is determined by the total wiring requirement. IN

terms of gate pitch, the total area required by the interconnect wiring can be

expressed as

Arequired = vAc (PlocLtotal_loc+PsemiLtotal_semi+PglobLtotal_glob)/N


Ac Chip area ;

N number of gates;

Ploc local pitch;

Psemi semi global pitch;

Pglobal global pitch;

Ltotal_loc total lengths of local interconnects;

Ltotal_semi total length of semi global interconnects;

Ltotal_glob total length of global interconnects;

The total interconnects length for any tier can be found by integrating the

wire-length distribution within the boundaries that define the tier. Hence it

follows that

Ltotal_loc= X ? li (l) dl

Ltotal_semi=X ? li (l) dl

Ltotal_glob = X ? li (l) dl

Where X is a correction factor that converts the point “to “ point interconnect

length to wiring net length (using a linear net model, X=4/(f.o. + 3)


This analysis is used to compare area and delay values for 2-D and 3-D

ICs. The availability of addition of silicon layers gives the designer extra

flexibility in trading off area with delay. A number of different cases are

discussed as follows:


1. Chip area minimization with fixed interconnect delay

Here, VILICs are assumed to consume negligible area, interconnect line

width is assumed to equal half the metal pitch at all times, and the total number

of metal layers for 2-D and 3-D case was conserved. A key assumption for the

geometrical construction of each tier of the multilevel interconnect network is

that all cross sectional dimensions are equal within that tier.

As Psemi increase from its value at the minimum Ac the semi global and

global pitches increase resulting in a larger wiring requirement and thus a larger

Ac. Furthermore, as Psemi increases, even longer wires can now satisfy the

maximum delay requirement in the semi global tier. These results in global wires

to be rerouted to the semi global tier, which in turn will require greater chip area.

Under such circumstances, the semi global tier begins to dominate and determine

the chip area. Conversely, as Psemi decreases from its value at the minimum Ac,

the longer wires in the semi global tier no longer satisfy the maximum delay

requirement of that tier and they need to be rerouted to the global tier where they

can enjoy a larger pitch. The populations of wires in global tiers increases and

since these wires have a large cross section they have a greater area requirement.

Under such circumstances the global tier begins to dominate and determine the

chip area.

The curve for the 3-D case has a minimum similar to the one obtained for

the can be observed that the minimum chip area for the 3-D case is

about Ë30% smaller than that of the 2-D case. Moreover, since the total wiring

requirement is reduced, the semi global tier pitch is reduced for the 3-Dchip. The

significant reductions in chip area demonstrated by the 3-D results are a

consequence of the fraction of wires that were converted from horizontal in 2-D

to vertical VILICs in 3-D. it is assumed that the area required by VILICs is



These results demonstrate, with given assumptions, that a 3-D IC can

operate at the same performance level, as measured by the longest wire delay, as

its 2-D counterpart while using up about 30% less silicon real estate. However, it

is possible for 3-D ICs to achieve greater performance than their 2-Dcounterparts

by reducing the interconnect impedance at the price of increased chip area as

discussed next.

2. Increasing Chip Area and Performance

3-D IC performance can be enhanced to exceed the performance of 2-D

ICs by improving interconnect delay. This is achieved by increasing the wire

pitch, which causes a reduction in the resistance. The effect of increasing psemi

and pglobal on the operating frequency and Ac.

This illustrates how the optimum semi global pitch (i.e., the psemi

associated with the minimum Ac) increases to obtain higher operating

frequencies. Also, as the semi global tier pitch increases, chip area and, therefore,

interconnect length also increases. However, we can see that the increase in chip

area still remains well below the area required for the 2-D case. The figure also

helps defines a maximum “ performance 3-D chip “ a chip with the same area as

the corresponding 2-D chip, which can be obtained by increasing the semi global

pitch beyond that for the 4-GHz case.

Two scenarios are considered 1) global pitch is increased to match the

global pitch for the 2-d case and 2) global pitch is increased to match the chip

area (footprint) for the 2-d case. Note that the delay requirements sets a

maximum values of interconnect length are given tier. Therefore, as interconnect

lengths are increased, lines which exceed this maximum length criterion for that

particular tier need to be rerouted on upper ties.

Beyond the maximum performance point for the 3-d chip, the

performance gain becomes increasingly smaller in comparison to the decrease in

performance resulting from the increase in chip area or reconnect delay.

Furthermore, as the semi global wires need to be rerouted on the global tiers,

which eventually leads to overcrowding of the global tier . Any further increases

in the wiring density in the global tier forces a reduction in the global pitch.


As the number of silicon layers increases beyond two, the assumption that

all interlayer interconnects (ILICs) are vertical and consume negligible area

becomes less tenable. The area used up by these horizontal ILICs can be

estimated from their total length and pitch.

The decrease in interconnect delay becomes progressively smaller as the

numbers of active layers increase. This is due to the fact that the area required by

ILICs begins to offset any area saving due to increasing the number of active



It is likely that there are local and semi global tiers associated with every

active layer, and a common global tier is used . This would result in an increase

in the total number of metal layers for the 3-D case. The effect of using 3-D case.

The effect of using 3-D ICs with constant metal layers and the effect of

employing twice the number of metal layers as in 2-D are summarized in the



It can be observed that by using twice the number of metal layers the

performance of the 3-D chip can be increased by an additional amount of 35% as

compared to the 3-d chip with the same total number of metal layers as in 2-d . It

can be observed that for the more aggressive technologies , the decrease in

interconnect delay from 2-D to 3-D case is less impressive. This indicates that

more than two active layers are possibly needed for those advanced nodes. The

figure also shows the impact of moving only the repeaters to the second layer Si

layer . It can also be observed that for more aggressive technologies , the

decrease in interconnect delay from 2-D to 3-D case is less impressive This

indicates that more than two active layers are possibly needed for those advanced



In estimating chip area, the metal requirement is calculated from the

obtained wire-length distribution. The total metallization requirement is

appropriately divided among the available metal layers in the corresponding


technology . Thus each tier , the local , the semi global and the global has three

metal layers . the resulting area of most densely packed tier determines the chip


Consequently, higher tier are routed within a larger than required area .

An optimization for this scenario is possible by rerouting some of the local wires

on the semi global tier and the latter on the global , without violating the

maximum allowable Length ( or delay ) per tier. This is achieved by reducing

the maximum allowed interconnect length for the local and semi global tiers.

Minimum chip area will achieved when all the tiers are equally congested. The

2-D chip area is seen to reduce by 9% as a result of this optimization is also

applied to applied to 3-D ICs .




An extremely important issue in 3-D ICs is heat dissipation. Thermal

effect s are already known to significantly impact interconnected /device

reliability and performance in high-performance 2-D ICs. The problem is

expected to be exacerbated by the reduction in chip size, assuming that same

power generated in a 2-D chip will now be generated in a smaller 3-D chip,

resulting in a sharp increase in the power and density Analysis of thermal

problems in 3-D circuits is therefore necessary to comprehend the limitations of

this technology and also to evaluate the thermal robustness of different 3-D

technology and design options.

It is well known that most of the heat energy in integrated circuits arises

due to transistor switching. This heat energy is typically conducted through the

silicon substrate to the package and then to the ambient by a heat sink .With

multi layer device designs, devices in the upper layer will also generate a

significant fraction of the heat .Furthermore, all the active layers will be

insulated from each other by layers of dielectrics (LTO, HSQ, polyamide, etc.)

which typically have much lower thermal conductivity than Si .Hence ,the heat

dissipation issue can become even more acute for 3-D ICs and can cause

degradation in device performance ,and reduction in chip reliability due to

increased junction leakage, electro migration failures ,and by accelerating other

failure mechanisms.



Three dimensional IC s will possibly introduce some new reliability

problems. These reliability issues may arise due to the electro thermal and

thermo mechanical effects between various active layers and the interfaces

between the active layers, which can also influence existing IC reliability hazards

such a electro migration and chip performance. Additionally, heterogeneous

integration of technologies using 3-d architecture will increase the need to

understand mechanical and thermal behavior of new material of new material

interfaces and thin film material thermal and mechanical properties.




A very popular method of fabricating a second active layer (Si) on top of

an existing substrate (oxidized Si wafer )is to deposit polysilicon and fabricate

thin film transistors (TFT). To enhance the performance of such transistors ,an

intense laser or electron beam is used to induce recrystalisation of the

polysilicon film to reduce or even eliminate most of the grain boundaries.


1. MOS on transistors fabricated on polysilicon exhibit very low surface

mobility values [of the order of 10 cm/Vs].

2. MOS transistors fabricated on polysilicon have high threshold voltages

(several volts) due to the high density of surface states (several 10 cm )

present at the grain boundaries.



1. This technique, however, may not be very practical for 3-D devices

because of the high temperature involved during melting of the


2. Difficulty in controlling the grain size variations.


Another technique for forming additional Si layers is to etch a hole in a

passivated wafer and epitaxially grow a single crystal Si seeded from open

window in the ILD. The Si crystal grows vertically and then laterally to cover

the ILD.


1. The quality of devices fabricated on these epitaxial layer can be as good

as those fabricated underneath on the seed wafer surface, since the grown

layer is single crystal with few defects.



1. The high temperatures involved in this process cause significant

degradation in the quality of devices on lower layers.


An attractive alternative is to bond two fully processed wafers on which

devices are fabricated on the surface ,including some interconnects, such that the

wafers completely overlap.Interchip vias are etched to electrically connect both

wafers after metallization and prior to the bonding process at 400 degree Celsius.

For applications where each chip is required to perform independent processing

before communicating with itâ„¢s neighbor , this technology can prove attractive .


1. Devices on all active levels have similar electrical properties.

2. Since all chips can be fabricated separately and later bonded ,there is

independence of processing temperature.


1. The lack of precision restricts the interchip communication to global metal



In this technique, a layer of amorphous Si is crystallized on top of the

lower active layer devices. The amorphous film is randomly crystallized to form

a polysilicon film. Device performance can be enhanced by eliminating the grain

boundaries in the polysilicon film. For this purpose ,local crystallization can be

induced using low temperatures processes (<600C) such as using patterned


seeding of germanium . In this method, Ge seeds implanted in narrow patterns

made on amorphous Si can be used to included lateral crystallization. This results

in the formation of small islands, which are nearly single crystal. CMOS

transistors can then be fabricated within these islands to give SOI like



1. This technique offers flexibility of creating multiple active layers

2. This is a low temperature technique



There is direct relation between improved chip performance and increased

utility of VILICs. It is therefore important to understand how to connect different

active layers with a reliable and compatible process. Upper layer processing

needs to be compatible with metal lines underneath connecting lower layer

devices and metal layers. With Cu technologies, this limits the processing

temperatures to <450 c for upper layers. Otherwise , Cu diffusion through barrier

layers , and the reliability and thermal stability of material interfaces can degrade

significantly. Tungsten is a refractory metal that can be used to withstand higher

processing temperatures, but it has higher resistivity. Current via technology can

also be employed to achieve VILIC functionality. The underlying assumption

here requires that interlayer gates are interconnected using regular horizontal

metal wires and vias, while interlayer interconnects can be VILICs connecting

the wiring network for each layer.


Recently, interlayer (VLIC)metallization schemes for 3-d ICs have been

demonstrated using direct wafer bonding. These techniques are based on the

bonding of two wafers with their active layers connected through vias ,which

serve as VILICs .

One method is based on the bonding of a thinned top wafer to a bottom

wafer with a organic adhesive layer of polyamide in between.

Interchip vias are etched through the ILD(inter level dielectric ),the

thinned top silicon wafer and through the cured adhesive layer ,with an approx

depth of 20 µm prior to the bonding process .the interconnect chip via made of

chemical wafer depositor (CVD). Tin liner and CVD-W plug provides a vertical

interconnect (VILIC)between the upper most metallization levels of both layers .

the bonding between the two wafers is done using a flip-chip bonder with split

beam optics at a temperature of 400 degree Celsius

A second technique realizes on the thermo compression bonding

between the metal parts in each wafer.

In this method, Cu-Ta pads on both wafers save as electrical contacts

between the interchips via on the top thinned silicon wafer and the upper most

interconnects on the bottom silicon wafer. The Cu-Ta pads can also function as

small bond pads for wafer bonding. Additionally, dummy metal patterns can be

made to increase the surface area for wafer bonding. The Cu-Ta bilayer pads

with a combined thickness of 700 nm are fused together by applying a

compressive force at 400 degree Celsius. This technique offers the advantage of

a metal “metal interface that will lower the interface thermal resistance between

the two wafers (and, hence, provide better conduction) and can be beneficial as a

partial ground plane for lowering the electromagnetic effects.


Many companies are working on the 3-D chips ,including groups at

Massachusetts institute of technology (MIT),international business

machines(IBM). Rensselar Polytechnic and SUNY Albany are also doing

research on techniques for bonding conventional chips together to form multiple

layers .whichever approach ultimately wins ,the multilayer chip building

technology opens up a whole new world of design .

However ,the Santa Clara, California US based startup company matrix

semiconductor will bring the first multilayer chip to the market ,while matrixâ„¢s

techniques will not likely result in more computing power ,they will produce

cheaper chips for certain applications, like memory used in digital cameras ,

personal digital assistants ,cellular phones ,hand held gaming devices ,etc .matrix

has adapted the technology developed for making flat “panel liquid crystal

displays to build chips with multilayer of circuitry.

The companyâ„¢s first products will be memory chips called 3-Dmemory,

for consumer electronics like digital cameras and audio players. current flash

memory cards for such devices are rewritable but expensive .however the newly

produced chips will cost ten times less, about as much as an audio tape or a roll

of film, but will only record information once. The cost is so largely because the

stacked chips contain the same amount of circuitry as flash cards but use a much

smaller area of the extremely expensive silicon wafers that form the basis for all

silicon chips. The chips will also offer a permanent record of the images and

sounds users record. The amount of computing power the company can

ultimately build in to its chips could be limited .the company hopes to eventually

build chips for cell phones, or low performance micro processors like those

found in appliances; such chips would be about one tenth as expensive as

current ones.


The patent technology opens up the ability to build ICs in three

dimensions- up as well as out in the horizontal directions as in the case now

with conventional chip designs. The result is a ten fold increase in the potential

no of bits on a silicon die, according to the company .moreover, the 3-D circuits

can be produced with todays standard semiconductor materials, fab equipments

and processors the 3-D memory will be used in memory devices which will be

marketed under well known brand names for portable electronics devices,

including digital cameras digital audio players, games, PDAs and archival

digital storage .the 3-D memory can also be used for pre recorded content such

as music, electronics books, digital maps, games, and reference guides.



Disks are inexpensive, but they requires drives that are expensive bulky

,fragile and consume a lot of battery power . Accidentally dropping a drive or

scratching a disk can cause significant damage and the potential loss of valuable

pictures and data. Flash and other non volatile memories are much more rugged,

battery efficient compact and require no bulky drive technologies . Dropping

them is not a problem they are however much more expensive. Both require the

use of a pc.

The ideal solution is a 3-D memory that leverages all the benefits of non

volatile media, costs as little as a disk, and is as convenient as 35 mm film and

audio tape.



Portable electronic digital cameras, digital audio players, PDAs, smart

cellular phones, and handheld gaming devices are among the fastest growing

technology market for both business and consumers. To date, one of the largest

constraints to growth has been affordable storage, creating the marketing

opportunity for ultra low cost internal and external memory. These applications

share characters beyond rapid market growth.

Portable devices all require small form factors ,battery efficiency,

robustness, and reliability. Both the devices and consumable media are extremely

price sensitive with high volumes coming only with the ability to hit low price

points. Device designers often trade application richness to meet tight cost

targets. Existing mask ROM and NAND flash non volatile technology force

designers and product planners to make the difficult choice between low cost or

field programmability and flexibility. Consumers value the convenience and ease

of views of readily available low cost storage. The potential to dramatically

lower the cost of digital storage weapons many more markets than those listed

above. Manufacturers of memory driven devices can now reach price points

previously inaccessible and develop richer, easier to use products.



Matrix is working with partners including Microsoft Corp, Thomas

Multimedia, Eastman Kodak and Sony Corp. three product categories are

planned: bland memory cards: cards sold preloaded with content, such as

software or music ; and standard memory packages, for using embedded

applications such as PDAs and set-top boxes .

Thomson electronics, the European electronic giant, will begin to

incorporate 3-D memory chips from matrix semiconductor in portable storage

cards, a strong endorsement for the chip start “up.

Thomson multimedia will incorporate the 3-D memory in memory cards

that cane be used to store digital photos or music. Although the cards plug into

cameras Thomson is also working on card readers that will allow consumers to

view digital photos on a television. The Thomson /matrix cards price makes the

difference from completing flash cards from Sony and Toshiba .the 64 MB

Thomson card will cost about as much as camera film does today. to further

strengthen the relationship with film ,the cards will be sold under the name

Technicolor Digital Memory Card.

Similar flash memory cards from other companies cost around Rs.1900 or

more-though consumers can erase and rerecord data on them, unlike the matrix

cards. As a result of their price, consumers buy very few of them. Thomson, by

contrast , expects to market its write-once cards in retail outlet such as Wal-


The first Technicolor cards will offer 64 MB of memory; version with 128

MB and 192 MB will appear later. The first 3-D chips will contain 64 MB.

Taiwan Semiconductor Manufacturing Co. is producing the chips on behalf of




The 3 D memory will just the first of a new generation of dense,

inexpensive chips that promise to make digital recording media both cheap and

convenient enough to replace the photographic film and audio tape. We can

understand that 3-D ICs are an attractive chip architecture, that can alleviate the

interconnect related problems such as delay and power dissipation and can also

facilitate integration of heterogeneous technologies in one chip. The multilayer

chip building technology opens up a whole new world of design like a city

skyline transformed by skyscrapers, the world of chips may never look at the

same again.



1. Proceedings of the IEEE, vol 89,no 5,may 2001:

(a) Jose E Schutt-Aine , sung-Mo Kang,

Interconnections “addressing the next challenge of IC technology at

page 583

(b) Robert h Have Mann, James A Hutch by,

High performance interconnects: an integration overview at page 586.

© Kaustav Banerjee, Shukri J Souri, Pawan Kapur and Krishna C Sara

swath 3-D ICs: a novel chip design for improving deep sub micrometer

interconnect performance and Soc integration at page 602.

2. Electronics today June 2002.



1. Introduction

2. Motivation for 3-D ICs

3. Scope of this study

4. Area and performance estimation of 3-D ICs

5. Challenges for 3-D Integration

6. Overview of 3-D IC technology

7. Present scenario of the 3-D IC industry

8. Advantages of 3-d memory

9. Applications of 3-D ICs

10. Future of 3-D IC industry

11. Conclusion

12. Reference
Use Search at wisely To Get Information About Project Topic and Seminar ideas with report/source code along pdf and ppt presenaion
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its difficult to read here please upload .doc file
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23-03-2011, 09:14 AM

Presented by:
Pouya Dormiani
Christopher Lucas

.ppt   3D.ppt (Size: 626.5 KB / Downloads: 77)
What is a 3D IC?
 Interconnect structures increasingly consume more of the power and delay budgets in modern design
 Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
 Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
• RC delay is increasingly becoming the dominant factor
 At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
 130 nm technology node, substantial interconnect delays will result.
• 3D Fabrication Technologies
 Many options available for realization of 3D circuits
 Choice of Fabrication depends on requirements of Circuit System
Performance Characteristics
 Timing
 Energy
 With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced
 In current technologies, timing is interconnect driven.
 Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
 The graph below shows the results of a reduction in wire length due to 3D routing
 Discussed more in detail later in the slides
Energy performance
 Wire length reduction has an impact on the cycle time and the energy dissipation
 Energy dissipation decreases with the number of layers used in the design
 Following graphs are based on the 3D tool described later in the presentation
 Energy performance graphs
Design tools for 3D-IC design
 Demand for EDA tools
• As the technology matures, designers will want to exploit this design area
 Current tool-chains
• Mostly academic
 We will discuss a tool from MIT
 3D Standard Cell tool Design
 3D Cell Placement
• Placement by min-cut partitioning
 3D Global Routing
• Inter-wafer vias
 Circuit layout management
3D Standard Cell Placement
 Natural to think of a 3D integrated circuit as being partitioned into device layers or planes
 Min cut part-itioning along the 3rd dimension is same as minimizing vias
 Total wire length vs. Vias
 Can trade off increased total wire length for fewer inter-plane vias by varying the point at which the design is partitioned into planes
• Plane assignment performed prior to detailed placement
 Yields smaller number of vias, but greater overall wire length
 Total wire length vs. Vias (Cont)
• Plane assignment not made until detailed placement stage
 Yields smaller total wire length but greater number of vias
Intro to Global Routing

• Global Routing involves generating a “loose” route for each net.
 Assigns a list of routing regions to a net without actually specifying the geometrical layout of the wires.
• Followed by detailed routing
 Finds the actual geometrical shape of the net within the assigned routing regions.
• Usually either sequential or hierarchical algorithms
Illustration of routing areas
 Hierarchical Global Routing
 Tool uses a hierarchical global routing algorithm
• Based on Integer programming and Steiner trees
• Integer programming approach still too slow for size of problem and complexity (NP-hard)
• Hierarchical routing methods break down the integer program into pieces small enough to be solved exactly
2D Global Routing
 A 2D Hierarchical global router works by recursively bisecting the routing substrate.
• Wires within a Region are fully contained or terminate at a pin on the region boundry.
 At each partitioning step the pins on the side of the routing region is allocated to one of the two subregions.
 Wires Connect cells on both sides of the partition line.
• These are cut by the partition and for each a pin is inserted into the side of the partition
 Once complete, the results can be fed to a detailed router or switch box router (A switchbox is a rectangular area bounded on all sides by blocks)
 Illustration of Bisection
Extending to 3D
 Routing in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.
• Wires can enter from any of the sides of the routing region in addition to its top and bottom
 3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias
 Basis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane.
• All we need now is enough area in the 2D routing space to route to the appropriate via
 3D Routing Results
 MAGIC is an open source layout editor developed at UC Berkeley
 3D-MAGIC is an extension to MAGIC by providing support for Multi-layer IC design
What’s different
• New Command :bond
• Bonds existing 2D ICs and places inter-layer Vias in the design file
• Once Two layers are bonded they are treated as one entity
Concerns in 3D circuit
 Thermal Issues in 3D-circuits
 Reliability Issues
Thermal Issues in 3D Circuits
 Thermal Effects dramatically impact interconnect and device reliability in 2D circuits
 Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density
 Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options.
Heat Flow in 2D
Heat Flow in 3D
Heat Dissipation

 All active layers will be insulated from each other by layers of dielectrics
 With much lower thermal conductivity than Si
 Therefore heat dissipation in 3D circuits can accelerate many failure mechanisms.
Heat Dissipation in Wafer Bonding versus Epitaxial Growth
 Wafer Bonding(b)
• 2X Area for heat dissipation
• Epitaxial Growth(a)
 Design 1
• Equal Chip Area
• Design 2
• Equal metal wire pitch
 High epitaxial temperature
EMI in 3D ICs
 Interconnect Coupling Capacitance and cross talk
• Coupling between the top layer metal of the first active layer and the device on the second active layer devices is expected
 Interconnect Inductance Effects
• Shorter wire lengths help reduce the inductance
• Presence of second substrate close to global wires might help lower inductance by providing shorter return paths
Reliability Issues?
 Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
 Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
Implications on Circuit Design and Architecture
 Buffer Insertion
 Layout of Critical Paths
 Microprocessor Design
 Mixed Signal IC’s
 Physical design and Synthesis
Buffer Insertion
• Use of buffers in 3D circuits to break up long interconnects
• At top layers inverter sizes 450 times min inverter size for the relevant technology
• These top layer buffers require large routing area and can reach up to 10,000 for high performance designs in 100nm technology
• With 3D technology repeaters can be placed on the second layer and reduce area for the first layer.

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