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27-09-2010, 10:42 AM

.pdf   VHDL-BASED MODELING OF A DC-DC BOOST CONVERTER.pdf (Size: 931.17 KB / Downloads: 114)

A VHDL-based description of a DC-DC boost converter is here presented. Starting from description of simple functional blocks such as voltage dividers, comparators and function's generators, more complex DC-DC step-up voltage converter was modeled by adopting a structural description of previous blocks. The proposed VHDL modeling can be used to simulate complex digital circuits which includes a few of analog parts (e.g., memory banks or DSP core) by adopting an event-driven standard simulator and avoiding using common transistor-level simulators which dramatically increase the verification time.VHDL or VHSIC-HDL (Very High Speed Integrated Circuit Hardware Description Language) is a hardware description language born about 20 years ago as a useful and efficient tool to modeling digital circuit [1], [2]. VHDL was initially designed to describes and simulate circuits whose behaviors can be preview through propagation of discrete signal values in a discrete time evolution. In order to well manage and verify the complex digital circuits in which some analog parts are instanced, in the last decade many researchers have been interested to extend VHDL toward the analog world [3], [4]. This because, a behavioral description of analog parts, allows to verify mainly-digital VLSI circuits by adopting again standard event-driven digital tools, without to resort to transistor-level simulators. Although already exists some analog extensions of VHDL, such as the VHDL-A [3] and VHDL-AMS [4], these languages have a time-scheduling simulation method like SPICE heavily increasing the overall verification time. As a consequence, it is useful to be able to simulate small analog parts inside a complex digital system using a pure event-driven tool. Today, literature presents many works in this direction [5]-[11], but many other fundamental analog blocks have never considered and modeled. In this paper a DC-DC boost converter will be describes and verifies using the VHDL language. The proposed description can be efficiently adopted in a mainly digital context, e.g., in digital signal processing cores as well as in memory systems, where these analog circuits are placed.

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08-10-2010, 10:34 PM

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