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Viterbi Decoder is a parameterizable high performance IP core that performs decoding of the convolutionally encoded data as well as punctured codes. The core is compatible with various standards such as DVB, 3G, WLAN, WIMAX IEEE 802.16d and 802.16e. This low latency decoder core supports various code rates, constraint lengths and generator polynomials and supports soft decision decoding. The core offers wireless Chipset designers, OEMâ„¢s and ODMâ„¢s a standard compliant platform to
accelerate development process and reduce time to market.
Â¢ Internal puncturing with puncturing clock : 1/2, 2/3, 3/4, 5/6
Â¢ Code rates : 1/2, 2/3, 3/4, 5/6
Â¢ Parameterizable trace back length and address width of the memory.
Â¢ Parameterizable width for soft decision from 1 to 8.
Â¢ Parameterizable constraint length from 3 to 9.
Â¢ Parameterizable generator polynomial.
Â¢ Data Format Offset Binary and Sign Magnitude
Â¢ Input Rate : 1/2
Â¢ Puncturing or non-puncturing the
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