vlsi technology based seminar or presentations
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VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.
The company was founded in 1979 by a trio from Fairchild Semiconductor by way of Synertek - Jack Balletto, Dan Floyd, Gunnar Wetlesen - and by Doug Fairbairn of Xerox PARC and Lambda (later VLSI Design) magazine.
Alfred J. Stein became the CEO of the company in 1982. Subsequently VLSI built its first fab in San Jose; eventually a second fab was built in San Antonio, Texas.
VLSI had its initial public offering in 1983, and was listed on the stock market as (NASDAQ: VLSI).
The company was later acquired by Royal Philips and survives to this day as part of NXP Semiconductors.
Advanced tools for VLSI design
A VLSI VL82C106 Super I/O chip.
The original business plan was to be a contract wafer fabrication company, but the venture investors wanted the company to develop IC design tools to help fill the foundry.
Thanks to its Caltech and UC Berkeley students, VLSI was an important pioneer in the electronic design automation industry. It offered a sophisticated package of tools, originally based on the 'lambda-based' design style advocated by Carver Mead and Lynn Conway.
VLSI became an early vendor of standard cell (cell-based technology) to the merchant market in the early 80s where the other ASIC-focused company, LSI Logic, was a leader in gate arrays. Prior to VLSI's cell-based offering, the technology had been primarily available only within large vertically integrated companies with semiconductor units such as AT&T and IBM.
VLSI's design tools eventually included not only design entry and simulation but eventually cell-based routing (chip compiler), a datapath compiler, SRAM and ROM compilers, and a state machine compiler. The tools were an integrated design solution for IC design and not just point tools, or more general purpose system tools. A designer could edit transistor-level polygons and/or logic schematics, then run DRC and LVS, extract parasitics from the layout and run Spice simulation, then back-annotate the timing or gate size changes into the logic schematic database. Characterization tools were integrated to generate FrameMaker Data Sheets for Libraries. VLSI eventually spun off the CAD and Library operation into Compass Design Automation but it never reached IPO before it was purchased by Avanti Corp.
VLSI's physical design tools were critical not only to its ASIC business, but also in setting the bar for the commercial EDA industry. When VLSI and its main ASIC competitor, LSI Logic, were establishing the ASIC industry, commercially-available tools could not deliver the productivity necessary to support the physical design of hundreds of ASIC designs each year without the deployment of a substantial number of layout engineers. The companies' development of automated layout tools was a rational "make because there's nothing to buy" decision. The EDA industry finally caught up in the late 1980s when Tangent Systems released its TanCell and TanGate products. In 1989, Tangent was acquired by Cadence Design Systems (founded in 1988).
Unfortunately, for all VLSI's initial competence in design tools, they were not leaders in semiconductor manufacturing technology. VLSI had not been timely in developing a 1.0 µm manufacturing process as the rest of the industry moved to that geometry in the late 80s. VLSI entered a long-term technology parthership with Hitachi and finally released a 1.0 µm process and cell library (actually more of a 1.2 µm library with a 1.0 µm gate).
As VLSI struggled to gain parity with the rest of the industry in semiconductor technology, the design flow was moving rapidly to a Verilog HDL and synthesis flow. Cadence acquired Gateway, the leader in Verilog hardware design language (HDL) and Synopsys was dominating the exploding field of design synthesis. As VLSI's tools were being eclipsed, VLSI waited too long to open the tools up to other fabs and Compass Design Automation was never a viable competitor to industry leaders.
Meanwhile, VLSI entered the merchant high speed static RAM SRAM market as they needed a product to drive the semiconductor process technology development. All the large semiconductor companies built high speed SRAMs with cost structures VLSI could never match. VLSI withdrew once it was clear that the Hitachi process technology partnership was working.
ARM Ltd was formed in 1990 as a semiconductor intellectual property licensor, backed by Acorn, Apple and VLSI. VLSI became a licensee of the powerful ARM processor and ARM finally funded processor tools. Initial adoption of the ARM processor was slow. Few applications could justify the overhead of an embedded 32 bit processor. In fact, despite the addition of further licensees, the ARM processor enjoyed little market success until they developed the novel 'thumb' extensions. Ericsson adopted the ARM processor in a VLSI chipset for its GSM handset designs in the early 1990s. It was the GSM boost that is the foundation of ARM the company/technology that it is today.
Only in PC chipsets, did VLSI dominate in the early 90s. This product was developed by five engineers using the 'Megacells" in the VLSI library that led to a business unit at VLSI that almost equaled its ASIC business in revenue. VLSI eventually ceded the market to Intel because Intel was able to package-sell its processors, chipsets, and even board level products together.
VLSI also had an early partnership with PMC, a design group that had been nurtured of British Columbia Bell. When PMC wanted to divest its semiconductor intellectual property venture, VLSI's bid was beaten by a creative deal by Sierra Semiconductor. The telecom business unit management at VLSI opted to go it alone. PMC Sierra became one of the most important telecom ASSP vendors.
Scientists and innovations from the 'design technology' part of VLSI found their way to Cadence Design Systems (by way of Redwood Design Automation). Compass Design Automation (VLSI's CAD and Library spin-off) was sold to Avant! Corporation, which itself was acquired by Synopsys.
Wikipedia, the free encyclopedia
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Microprocessors are essential to many of the products we use every day such as TVs, cars, radios, home appliances and of course, computers. Transistors are the main components of microprocessors.At their most basic level, transistors may seem simple. But their development actually required many years of painstaking research. Before transistors, computers relied on slow, inefficient vacuum tubes and mechanical switches to process information. In 1958, engineers managed to put two transistors onto a Silicon crystal and create the first integrated circuit, which subsequently led to the first microprocessor.
Transistor size: Intel’s research labs have recently shown the world’s smallest transistor, with a gate length of 15nm. We continue to build smaller and smaller transistors that are faster and faster. We've reduced the size from 70 nanometer to 30 nanometer to 20 nanometer, and now to 15 nanometer gates.
Manufacturing process: A new manufacturing process called 130 nanometer process technology (a nanometer is a billionth of a meter) allows Intel today to manufacture chips with circuitry so small it would take almost 1,000 of these "wires" placed side-by-side to equal the width of a human hair. This new 130-nanometer process has 60nm gate-length transistors and six layers of copper interconnect. This process is producing microprocessors today with millions of transistors and running at multi-gigahertz clock speeds.
Wafer size: Wafers, which are round polished disks made of silicon, provide the base on which chips are manufactured. Use a bigger wafer and you can reduce manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches) diameter silicon wafer size, up from the previous wafer size of 200mm (about 8 inches).
Digital logic is implemented using transistors in integrated circuits containing many gates.
small-scale integrated circuits (SSI) contain 10 gates or less
medium-scale integrated circuits (MSI) contain 10-100 gates
large-scale integrated circuits (LSI) contain up to 104 gates
very large-scale integrated circuits (VLSI) contain >104 gates
Improvements in manufacturing lead to ever smaller transistors allowing more per chip.
>107 gates/chip now possible; doubles every 18 months or so
Variety of logic families
TTL - transistor-transistor logic
CMOS - complementary metal-oxide semiconductor
ECL - emitter-coupled logic
GaAs - gallium arsenide
What are shown on previous diagrams cover only the so called front‑end
processing ‑ fabrication steps that go towards forming the devices and
inter‑connections between these devices to produce the functioning IC's. The end result are wafers each containing a regular array of the same IC chip or die. The wafer then has to be tested and the chips diced up and the good chips mounted and wire‑bonded in different types of IC package and tested again before being shipped out.
Gordon E. Moore - Chairman Emeritus of Intel Corporation
1965 - observed trends in industry - # of transistors on ICs vs. release dates:
Noticed number of transistors doubling with release of each new IC generation
release dates (separate generations) were all 18-24 months apart
The number of transistors on an integrated circuit will double every 18 months
The level of integration of silicon technology as measured in terms of number of devices per IC
This comes about in two ways – size reduction of the individual devices and increase in the chip or dice size
As an indication of size reduction, it is interesting to note that feature size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early 1970’s, whereas now all features are measured in mm’s (1 mm = 10-6 m or 10-4 cm)
Semiconductor industry has followed this prediction with surprising accuracy
Limits of Moore’s Law?
Growth expected until 30 nm gate length (currently: 180 nm)
size halved every 18 mos. - reached in
2001 + 1.5 log2((180/30)2) = 2009
Paradigm shift needed in fabrication process
Technological Background of the Moore’s Law
To accommodate this change, the size of the silicon wafers on which the integrated circuits are fabricated have also increased by a very significant factor – from the 2 and 3 in diameter wafers to the 8 in (200 mm) and 12 in (300 mm) diameter wafers
The latest catch phrase in semiconductor technology (as well as in other material science) is nanotechnology – usually referring to GaAs devices based on quantum mechanical phenomena
These devices have feature size (such as film thickness, line width etc) measured in nanometres or 10-9 metres
Very Large Scale Integration
design/manufacturing of extremely small, complex circuitry using modified semiconductor material integrated circuit (IC) may contain millions of transistors, each a few mm in size applications wide ranging: most electronic logic devices.
Origins of VLSI
Much development motivated by WWII need for improved electronics, especially for radar
1940 - Russell Ohl (Bell Laboratories) - first pn junction
1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor
1956 Nobel Physics Prize
Late 1950s - purification of Si advances to acceptable levels for use in electronics
1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604
1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm2
1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit
1968 - Noyce, Gordon E. Moore found Intel
1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm2
Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law
Three Dimensional VLSI
The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensions
The vertical orientation of several bare integrated circuits in a single package
Noise - unwanted disturbances on a useful signal
reflection noise (varying impedance along interconnect)
crosstalk noise (interference between interconnects)
electromagnetic interference (EMI) (caused by current in pins)
3D chips fewer, shorter interconnect sfewer pins.
Advantages of 3D VLSI
Printed circuit board size/weight
planar size of PCB reduced with negligible IC height increase
weight reduction due to more circuitry per package/smaller PCBs
estimated 40-50 times reduction in size/weight
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